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| author | Bent Bisballe Nyeng <deva@aasimon.org> | 2018-01-23 20:53:40 +0100 |
|---|---|---|
| committer | Bent Bisballe Nyeng <deva@aasimon.org> | 2018-01-23 20:53:40 +0100 |
| commit | a23e928a1f4424d3e7c6a1fdb4883f5dbd46fba2 (patch) | |
| tree | ca50cc8a9f629efcbb947416b7bfbcaf104bb79c | |
| parent | 745625c8b633c1b0db285cc89791f44c731b3be0 (diff) | |
Add vhd2vl VHDL to Verilog conversion tool.
| -rwxr-xr-x | fpga-toolchain/build.sh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga-toolchain/build.sh b/fpga-toolchain/build.sh index 57d06fe..e052da0 100755 --- a/fpga-toolchain/build.sh +++ b/fpga-toolchain/build.sh @@ -66,4 +66,18 @@ then popd fi +# Couldn't get it to compile... +#D=yodl +#SRC=https://github.com/forflo/yodl.git + +D="vhd2vl" +if [ ! -d $D ] +then + git clone https://github.com/ldoolitt/vhd2vl.git $D + pushd $D/src + make + cp vhd2vl $ROOT/install/bin + popd +fi + popd |