From e8456a1537c6541f8b59a46493ab352c757f84ef Mon Sep 17 00:00:00 2001 From: Jonas Suhr Christensen Date: Tue, 30 Jan 2018 20:49:11 +0100 Subject: fpga/experiments: add blinky vhdl example shift register --- fpga-toolchain/experiments/blinky.vhdl | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 fpga-toolchain/experiments/blinky.vhdl diff --git a/fpga-toolchain/experiments/blinky.vhdl b/fpga-toolchain/experiments/blinky.vhdl new file mode 100644 index 0000000..523248b --- /dev/null +++ b/fpga-toolchain/experiments/blinky.vhdl @@ -0,0 +1,44 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity top is + Port ( + hwclk : in STD_LOGIC; + mosi : in STD_LOGIC; + led1 : out STD_LOGIC; + led2 : out STD_LOGIC; + led3 : out STD_LOGIC; + led4 : out STD_LOGIC; + led5 : out STD_LOGIC; + led6 : out STD_LOGIC; + led7 : out STD_LOGIC; + led8 : out STD_LOGIC + ); + +end top; + +architecture Behavioral of top is + + signal shift_reg : STD_LOGIC_VECTOR(8 downto 0); + +begin + +led1 <= shift_reg(0); +led2 <= shift_reg(1); +led3 <= shift_reg(2); +led4 <= shift_reg(3); +led5 <= shift_reg(4); +led6 <= shift_reg(5); +led7 <= shift_reg(6); +led8 <= shift_reg(7); + +process (clk) +begin +if (rising_edge(CLK)) then + shift_reg(8 downto 1) <= shift_reg(7 downto 0); +end if; +end process; + +end Behavioral; -- cgit v1.2.3