From de61e148f79ec0a0756bb34557a2a025db7fd1cf Mon Sep 17 00:00:00 2001 From: Jonas Suhr Christensen Date: Tue, 30 Jan 2018 21:14:51 +0100 Subject: fpgs/blinky: update vhdl example --- fpga-toolchain/experiments/blinky.vhdl | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/fpga-toolchain/experiments/blinky.vhdl b/fpga-toolchain/experiments/blinky.vhdl index 523248b..7eb52f6 100644 --- a/fpga-toolchain/experiments/blinky.vhdl +++ b/fpga-toolchain/experiments/blinky.vhdl @@ -14,14 +14,15 @@ entity top is led5 : out STD_LOGIC; led6 : out STD_LOGIC; led7 : out STD_LOGIC; - led8 : out STD_LOGIC + led8 : out STD_LOGIC; + outnext : out STD_LOGIC ); end top; architecture Behavioral of top is - signal shift_reg : STD_LOGIC_VECTOR(8 downto 0); +signal shift_reg : STD_LOGIC_VECTOR(7 downto 0); begin @@ -33,12 +34,19 @@ led5 <= shift_reg(4); led6 <= shift_reg(5); led7 <= shift_reg(6); led8 <= shift_reg(7); +outclk <= hwclk; -process (clk) +process (hwclk) begin -if (rising_edge(CLK)) then - shift_reg(8 downto 1) <= shift_reg(7 downto 0); +if (rising_edge(hwclk)) then + shift_reg(7 downto 0) <= shift_reg(6 downto 0) & mosi; end if; end process; +a:process (hwclk) +begin +if (falling_edge(hwclk)) then + outnext <= shift_reg(7); +end if; +end process; end Behavioral; -- cgit v1.2.3