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| author | Bent Bisballe Nyeng <deva@aasimon.org> | 2018-01-23 20:53:40 +0100 |
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| committer | Bent Bisballe Nyeng <deva@aasimon.org> | 2018-01-23 20:53:40 +0100 |
| commit | a23e928a1f4424d3e7c6a1fdb4883f5dbd46fba2 (patch) | |
| tree | ca50cc8a9f629efcbb947416b7bfbcaf104bb79c /fpga-toolchain/experiments/pinmap.pcf | |
| parent | 745625c8b633c1b0db285cc89791f44c731b3be0 (diff) | |
Add vhd2vl VHDL to Verilog conversion tool.
Diffstat (limited to 'fpga-toolchain/experiments/pinmap.pcf')
0 files changed, 0 insertions, 0 deletions